1. Field of the Invention
The present invention relates to phase-locked loop (“PLL”) circuits, and, more particularly, to a fractional-integer PLL circuit. More specifically, the present invention relates to a fractional-integer PLL circuit having a fractional-frequency-interval phase frequency detector.
2. Description of Related Art
A phase-locked loop (“PLL”) circuit generally includes a phase detector, a loop filter, and a controlled oscillator. The phase detector receives an input signal, which has a reference frequency. The output signal of the controlled oscillator is fed back to the phase detector. The frequency of the output signal is typically a multiple of the reference frequency of the input signal. The PLL circuit is utilized to lock the output frequency to the input frequency. Locking the output frequency to the input reference frequency is critical in various applications, such as developing accurate and precise clocks for digital signal processors (“DSPs”) and for audio sampling frequencies and rates. Fast locking applications also exist in which adaptive bandwidth PLLs have been developed and used.
However, certain applications in the electronics field require the use of fractional multiples instead of integer multiples of a reference clock frequency. Fractional-N phase locked loops (PLLs) have been developed and utilized to provide fractional multiples of a reference frequency for such applications. One way of providing a fractional-N PLL is to dynamically switch the divider module of the PLL between two integer values to provide the desired fractional integer. However, dynamic switching of the divider module between two integer values increases the phase noise that is introduced into the PLL. For example, for each reference period, a difference between the actual divider module value and an average ideal value represents an error that is injected into the PLL, which results in increased phase noise.
A delta-sigma fractional-N PLL wherein fractional-N is a fractional integer overcomes at least the white noise problem by having a digital delta-sigma modulator provide a sequence for the divider module such that the quantization noise is in a frequency band well above a desired bandwidth of the PLL. A delta-sigma fractional-N PLL is similar to an integer-N PLL, but the delta-sigma fractional-N PLL has additional digital circuitry for interpolating between integer multiples of the reference frequency.
FIG. 1 shows a block diagram of an exemplary delta-sigma fractional-N phase-locked loop (PLL) circuit 100 according to the prior art. Loop filter 100 includes a phase frequency detector 104, a charge pump 106, a loop filter 108, and a voltage-controlled oscillator (VCO) 110 coupled together in series as shown in FIG. 1. Input reference clock signal 103 is fed into a positive input node of phase frequency detector 104.
An N divider 112 is coupled in the feedback loop of delta-sigma fractional-N PLL circuit 100. The feedback loop consists of an output signal 116 of PLL circuit 100 fed into an N divider 112 as shown in FIG. 1. N divider 112, in effect, divides output signal 116 by a factor of N to provide an input feedback signal 113. The N-divided input feedback signal 113 is fed back as an input signal into the negative input node of phase frequency detector 104. Input feedback signal 113 is also fed into digital delta-sigma modulator 114. Delta-sigma modulator 114 allows output signal 116 to be divided by a divider value between integer multiple values of N and another integer (e.g., N−1 and/or N+1) based on the ratio input 111 received. Ratio input 111 is utilized to define a fractional value for the desired fractional-integer. Modulated output signal 115 from digital delta-sigma modulator 114 is fed into N divider 112. Digital delta-sigma modulator 114 allows output signal 116 to be divided by a divider value that is just between integer values (e.g., the integer value N and another integer value N−1 and/or N+1) to provide the desired fractional value. Digital delta-sigma modulator 114 also provides the sequence for N divider 112 such that the quantization noise is in a frequency band well above a desired bandwidth of PLL circuit 100.
The present invention recognizes the desire and need for providing a fractional-integer PLL circuit having a wider bandwidth and a higher, more desired corner frequency. The present invention further recognizes the desire and need to provide a fractional-integer PLL that reduces or eliminates non-linear errors that tend to cause out-of-band modulator quantization noise to be folded into low frequencies. The present invention also recognizes the need and desire for a fractional-integer PLL that minimizes or avoids the introduction of additional noise and errors. The present invention additionally recognizes the need and desire for a fractional-integer PLL that is not limited to just modulating between integer divider values. The present invention overcomes the problems and disadvantages in accordance with the prior art.